The present disclosure relates to a signal receiving apparatus, a signal receiving method and a signal receiving program. More particularly, the present disclosure relates to a signal receiving apparatus having a small circuit scale for a case in which Fourier-transform results and inverse-Fourier-transform results are demanded in signal processing carried out by the apparatus, and relates to a signal receiving method adopted by the apparatus as well as a signal receiving program implementing the method.
As a modulation method of the ground digital broadcasting, an OFDM (Orthogonal Frequency Division Multiplexing) method is adopted. The OFDM method is a method for modulating each of a number of orthogonal carrier waves by adoption of a PSK (Phase Shift Keying) technique or a QAM (Quadrature Amplitude Modulation) technique. In a signal receiving apparatus for receiving a broadcast signal obtained as a result of modulation carried out by adoption of typically the OFDM method, Fourier-transform processing and inverse-Fourier-transform processing are carried out in order to demodulate data conveyed by the signal.
FIG. 1 is a block diagram showing a demodulation section 1 employed in the existing signal receiving apparatus.
As shown in FIG. 1, the demodulation section 1 is configured to include a Fourier-transform processing block 11, a signal division block 12, a noise detection block 13, an inverse-Fourier-transform processing block 14, a channel inference block 15 and a Fourier-transform processing block 16. In the existing signal receiving apparatus, an IF (Intermediate Frequency) signal is subjected to an orthogonal demodulation process carried out by making use of a carrier signal having a frequency determined in advance. A baseband OFDM signal obtained as a result of the orthogonal demodulation process is then supplied to the Fourier-transform processing block 11.
The OFDM signal supplied to the Fourier-transform processing block 11 is a time-domain signal prior to execution of FFT (Fast Fourier Transform) processing. As a result of the orthogonal demodulation process carried out by the existing signal receiving apparatus, the OFDM time-domain signal supplied to the Fourier-transform processing block 11 is changed to a signal having a real-axis component referred to as an I signal and an imaginary-axis component referred to as a Q signal. That is to say, as a result of the orthogonal demodulation process, the OFDM time-domain signal supplied to the Fourier-transform processing block 11 becomes a signal which is a combination of data transmitted by a signal transmitting apparatus and an impulse response representing a channel state.
The Fourier-transform processing block 11 is a block for carrying out Fourier transform on the OFDM time-region signal in order to produce a signal representing a result of the Fourier transform. The signal output by the Fourier-transform processing block 11 to the signal division block 12 is a frequency-domain signal obtained as a result of the Fourier transform.
The signal division block 12 is a block for dividing the frequency-domain signal received from the Fourier-transform processing block 11 by a signal received from the Fourier-transform processing block 16 in order to get rid of distortion components of the channel. The signal division block 12 supplies the frequency-domain signal obtained as a result of the division process carried out by the signal division block 12 in order to get rid of the distortion components to the noise detection block 13 and sections provided at the later stage following the demodulation section 1. The sections provided at the later stage following the demodulation section 1 include an error correction section.
The noise detection block 13 is a block for detecting noise components included in the frequency-domain signal received from the signal division block 12 and outputting a signal representing the result of the noise-component detection to the inverse-Fourier-transform processing block 14.
The inverse-Fourier-transform processing block 14 is a block for carrying out inverse Fourier transform on the frequency-domain signal received from the noise detection block 13 and outputting a signal representing the result of the inverse Fourier transform to the channel inference block 15. The signal output by the inverse-Fourier-transform processing block 14 is a time-domain signal.
The channel inference block 15 is a block for inferring the state of the channel on the basis of the time-domain signal received from the inverse-Fourier-transform processing block 14 and outputting a time-domain signal representing the result of the inference to the Fourier-transform processing block 16. As the result of the processing to infer the state of the channel, the channel inference block 15 outputs the time-domain signal representing the positions of a main path, a pre-echo and a post-echo which are included in a segment determined in advance.
The Fourier-transform processing block 16 is a block for carrying out Fourier transform on the time-domain signal received from the channel inference block 15 and outputting a frequency-domain signal representing the result of the Fourier transform to the signal division block 12.
As described above, in the demodulation section 1, in order to equalize the signal output by the Fourier-transform processing block 11, the inverse-Fourier-transform processing block 14 carries out the inverse Fourier transform whereas the Fourier-transform processing block 16 carries out the Fourier transform.
FIG. 2 is a block diagram showing the configuration of the Fourier-transform processing block 16 employed in the demodulation section 1 shown in FIG. 1.
As shown in FIG. 2, the Fourier-transform processing block 16 is configured to include a control unit 21, an input memory 22, a Fourier-transform execution unit 23 and an output memory 24. The Fourier-transform processing block 16 receives pieces of data represented by the time-domain signal output from the channel inference block 15 as data to serve as an object of the Fourier transform.
The Fourier-transform data x (n) is stored at an address n in the input memory 22. In this case, n denotes a point of time. n=0 indicates a point of time at which the first Fourier-transform data x (0) is stored. The control unit 21 specifies the address n at which Fourier-transform data x (n) is stored.
N is a data count which is the number of pieces of data to serve as an object of the Fourier transform. When N pieces of data to serve as an object of the Fourier transform have been stored in the input memory 22, the Fourier-transform execution unit 23 carries out the Fourier transform on the data. The Fourier transform carried out by the Fourier-transform execution unit 23 is represented by Eq. (1) given as follows.
                              X          ⁡                      (            k            )                          =                              ∑                          n              =              0                                      N              -              1                                ⁢                                    x              ⁡                              (                n                )                                      ⁢                          ⅇ                                                -                  j                                ⁢                                                                  ⁢                2                ⁢                π                ⁢                                                                  ⁢                                  nk                  N                                                                                        (        1        )            
In Eq. (1), notation j denotes the imaginary-number unit. x (n), where n=0, 1, . . . and (N−1), denotes Fourier-transform data stored in the input memory 22. X (k), where k=0, 1, . . . and (N−1), denotes results of the Fourier transform. It is to be noted that, depending on the data count N, Eq. (1) can be modified to a simple equation representing simple Fourier transform. However, explanation of the simple equation and the simple Fourier transform is omitted.
N results X (k) of the Fourier transform carried out by the Fourier-transform execution unit 23 are stored at addresses k in the output memory 24. The addresses k are also specified by the control unit 21.
After all the N results X (k) of the Fourier transform have been stored at respectively addresses 0 to (N−1) in the output memory 24, the N results X (k) are read out sequentially from the addresses 0 to (N−1). The address from which a result of the Fourier transform is read out from the output memory 24 is also specified by the control unit 21. To put it concretely, the results X (0), X (1), . . . and X (N−1) are read out from the output memory 24 in the frequency-index order.
FIG. 3 is a block diagram showing the configuration of the inverse-Fourier-transform processing block 14 employed in the demodulation section 1 shown in FIG. 1.
As shown in FIG. 3, the inverse-Fourier-transform processing block 14 is configured to include a control unit 31, an input memory 32, an inverse-Fourier-transform execution unit 33 and an output memory 34. The inverse-Fourier-transform processing block 14 receives pieces of data represented by the frequency-domain signal output from the noise detection block 13 as data to serve as an object of the inverse Fourier transform.
The inverse-Fourier-transform data Y (k) is stored at an address k in the input memory 32. In this case, k denotes a frequency index. k=0 indicates the frequency index of the first inverse-Fourier-transform data Y (0). The control unit 31 specifies the address k at which inverse-Fourier-transform data Y (k) is stored.
N is a data count which is the number of pieces of data to serve as an object of the inverse Fourier transform. When N pieces of data to serve as an object of the inverse Fourier transform have been stored in the input memory 32, the inverse-Fourier-transform execution unit 33 carries out the inverse Fourier transform on the data. The inverse Fourier transform carried out by the inverse-Fourier-transform execution unit 33 is represented by Eq. (2) given as follows.
                              y          ⁡                      (            n            )                          =                              ∑                          k              =              0                                      N              -              1                                ⁢                                    Y              ⁡                              (                k                )                                      ⁢                          ⅇ                              j                ⁢                                                                  ⁢                2                ⁢                π                ⁢                                                                  ⁢                                  nk                  N                                                                                        (        2        )            
In Eq. (2), notation j denotes the imaginary-number unit. Y (k), where k=0, 1, . . . and N−1, denotes inverse-Fourier-transform data stored in the input memory 32. y (n), where n=0, 1, . . . and N−1, denotes results of the inverse Fourier transform. It is to be noted that, depending on the data count N, Eq. (2) can be modified to a simple equation representing simple inverse Fourier transform. However, explanation of the simple equation and the simple inverse Fourier transform is omitted.
N results y (n) of the inverse Fourier transform carried out by the inverse-Fourier-transform execution unit 33 are stored at addresses n in the output memory 34. The addresses n are also specified by the control unit 31.
After all the N results y (n) of the inverse Fourier transform have been stored at respectively addresses 0 to (N−1) in the output memory 34, the N results y (n) are read out sequentially from the addresses 0 to (N−1). The address from which a result of the inverse Fourier transform is read out from the output memory 34 is also specified by the control unit 31. To put it concretely, the results y (0), y (1), and y (N−1) are read out sequentially from the output memory 24.
For more information, the reader is suggested to refer to Japanese Patent Laid-Open No. 2009-164746.